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fifo程序
- 用verilog语言在fpga中实现fifo功能！-using Verilog language in which they simply realize fifo function!
异步FIFO存储器的控制设计
- 异步FIFO控制器的设计 主要用于异步先进先出控制器的设计。 所用语言Verilog HDL.-asynchronous FIFO controller design for the main asynchronous FIFO controller design. The language used Verilog HDL.
verilog.HDL.examples
- 许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等-many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
fifo_ver_131
- fifo verilog hdl 源程序-fifo verilog hdl source
FIFO
- 一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows
FIFO_v
- FIFO的verilog实现，内附testbench和文档说明-FIFO verilog achieve, enclosing testbench and documentation shows
FIFO
- 异步FIFO控制器的Verilog设计与实现
FIFO-DC
- FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合
fifo
- 高速FIFO，verilog设计。速度高达130Mhz
fifo
- 使用Verilog语言编写，把FPGA配置成一个fifo
fifo-ram
- 采用Verilog语言描述的FIFO和双端口RAM源代码。
FIFO
- verilog开发的FIFO，经过验证，有完整版本的测试程序，经典之作
fifo
- 基于verilog HDL的fifo设计与测试，包含设计与测试代码，以及简单的makefile编写。整个平台是基于linux操作，仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
FIFO
- FIFO code in verilog
异步FIFO
- 自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
FIFO
- FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA FIFO example, reading and writing FIFO in FPGA chip.)
fifo
- Verilog HDL实现通用的FIFO的一个demo，可以参考这个程序根据自己的需求更改深度和宽度，以及标志位(Verilog HDL implements a demo of a generic FIFO that you can refer to to to change the depth and width, as well as the flag bits, depending on your needs)
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
异步FIFO
- 纯Verilog实现的异步FIFO，分为读写控制模块，SRAM CORE，同步等几个模块，内含源文件和仿真文件(The asynchronous FIFO implemented by Verilog is divided into read-write control module, SRAM core module and synchronization module)